In this letter, we discuss the problem of receive antenna selection in the downlink of multiuser multiple-input multiple-output (MIMO) systems with Tomlinson-Harashima precoding (THP), where the number of receivers is assumed equal to that of transmit antennas. Based on the criterion of maximum system sum-capacity, a per-layer receive antenna selection scheme is proposed. This scheme, which selects one receive antenna for each receiver, can well exploit the nonlinear and successive characteristics of THP. Two models are established for the proposed per-layer scheme and the conventional per-user scheme. Both the theoretical analysis and simulation results indicate that the proposed scheme can greatly improve the equivalent channel power gains and the system sum-capacity.

In this letter, we propose an efficient user selection algorithm aiming to select users with less spatially correlation and meet the user number limit of zero-forcing beamforming in downlink multiuser MIMO systems. This algorithm yields a considerable complexity reduction with only a small loss in performance and it only needs partial users' CSI feedback. Coupled with the algorithm, a null space updating method in O(K2) time and a modified proportional fair scheduling algorithm are also proposed.

In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. By taking the advantages of both layered scheduling and fully-parallel architecture, the decoder can fully support multi-mode decoding specified in WiMAX with the parallelism much higher than commonly used partial-parallel layered LDPC decoder architecture. 6-bit quantized messages are split into bit-serial style and 2bit-width serial processing lines work concurrently so that only 3 cycles are required to decode one layer. As a result, 12∼24 cycles are enough to process one iteration for all the code-rates specified in WiMAX. Compared to our previous bit-serial decoder, it doubles the parallelism and solves the message saturation problem of the bit-serial arithmetic, with minor gate count increase. Power synthesis result shows that the proposed decoder achieves 5.83pJ/bit/iteration energy efficiency which is 46.8% improvement compared to state-of-the-art work. Furthermore, an advanced dynamic quantization (ADQ) technique is proposed to enhance the error-correcting performance in layered decoder architecture. With about 2% area overhead, 6-bit ADQ can achieve the error-correcting performance close to 7-bit fixed quantization with improved error floor performance.

In this paper, we used the data set of domain names Global Top 1M provided by Alexa to analyze the effectiveness of Fallback in ECN. For the same test server, we first negotiate a connection with Not-ECN-Capable, and then negotiate a connection with ECN-Capable, if the sender does not receive the response to ECN-Capable negotiation from the receiver by the end of retransmission timeout, it will enter the Fallback state, and switch to negotiating a connection with Not-ECN-Capable. By extracting the header fields of the TCP/IP packets, we confirmed that in most regions, connectivity will be slightly improved after Fallback is enabled and Fallback has a positive effect on the total time of the whole access process. Meanwhile, we provided the updated information about the characteristics related to ECN with Fallback in different regions by considering the geographical region distribution of all targeted servers.

TCP Friendly Rate Control (TFRC) has been widely used in the Internet multimedia streaming applications. However, performance of traditional TFRC algorithm degrades significantly when deployed over wireless networks. Although numerous TFRC variants have been proposed to improve the performance of TFRC over wireless networks, designing a TFRC algorithm with graceful performance both in throughput and fairness still remains a great challenge. In this paper, a novel TFRC algorithm, named TFRC-FIT, is proposed to improve the performance of TFRC over wireless environments. In the proposed approach, the behavior of multiple TFRC flows is simulated in single connection, while the number of simulated flows is adjusted by the network queuing delay. Through this mechanism, TFRC-FIT can fully utilize the capacity of wireless networks, while maintaining good fairness and TCP friendliness. Both theoretical analysis and extensive experiments over hardware network emulator, Planetlab test bed as well as commercial 3G wireless networks are carried out to characterize and validate the performance of our proposed approach.

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 2448 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36 mm2 in SMIC 65 nm CMOS process, and realizes 1056 Mbps throughput at 1.2 V, 110 MHz and 10 iterations with 115 mW power occupation, which infers a power efficiency of 10.9 pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.